1. Technical Field
The present invention relates generally to apparatus and methods for transmitting signals between nodes, and more particularly for transmitting signals at high bit-rates between nodes.
2. Background
A typical computer or inter-linked set of computers can be modeled as a series of nodes which communicate with one another point-to-point. Although nodes have in the past been attached to a bus, modern communications standards more commonly employ point-to-point interconnections. In the past, the communication data rate between such nodes was limited more by the performance of the computer or its various internal chips than by the speed of the traces or transmission lines by which the nodes were connected. Now as chip and computer speeds have substantially increased, these interconnects are hindering further performance improvements.
More specifically, current signaling architectures as well as the physical limitations of the traces and transmission lines themselves limit the maximum inter-node communications rate. Synchronized buses and point-to-point links are two of interconnect architectures commonly used. Synchronous bus architectures typically broadcast an address block to all nodes on a multiplexed bus. The node corresponding to the address then generates an acknowledgement block, which is also broadcast to all of the nodes. This architecture results in relatively low communications throughput. This is because each node must be synchronized to the same common reference clock so that address and acknowledgment blocks can be transmitted and received. Nodes employing the synchronous bus architecture must also take turns communicating, further limiting the maximum possible inter-node data rate, especially when a large number of nodes are connected to the same bus. The multiplexed buses used with synchronous bus architectures also typically contain intermediate stubs and additional signal paths that limit the effective speed of data transfer between nodes.
Point-to-point link architectures are comparatively more time efficient since their signals have an affiliated reference clock signal. Using a point-to-point link architecture, two nodes can transfer data at a rate independent of other nodes and of any common reference clock. However, point-to-point link inter-node data rates still tend to be limited by the physical limitations in the traces and transmission lines.
For instance, modern computers typically communicate by either single-ended or differential signaling. Both of these forms of signaling are well known in the art. Ideally, single-ended connections require only one physical line per logic signal. However, as communication rates have increased so has ground-bounce, which is inherent in single-ended systems. Attempts to solve the ground-bounce problem include adding power supply and ground pins for each single-ended logic line on a chip, effectively tripling the number of physical traces required. Thus, six single-ended logic signals can require up to eighteen physical traces. Differential signaling systems require two physical traces for each logic signal. Thus, six differential logic signals require at least twelve physical traces. Since silicon and computer resources are finite, a large number of traces or transmission lines can significantly increase the cost of manufacturing the chip or the computer.
Regardless of whether single-ended or differential signaling is used, the physical traces and transmission lines all have an inherent parasitic inductance. As the data rate over these pathways increases, the parasitic inductance combined with the quickly varying signal currents generate parasitic voltages that interfere with and corrupt the signals traveling over these pathways.
Additionally, large signal currents that pass through the traces and transmission lines can generate Electro-Magnetic Interference (EMI) noise which further corrupts signals traveling between the nodes. Such EMI noise may also, from time to time, exceed the limits of various well known regulatory standards for permissible EMI radiation levels.
Other prior art approaches have employed RAMBUS technology (manufactured by RAMBUS, Inc. of Mountain View, Calif.) to reduce the parasitic and EMI noise voltages present on some signal lines. The RAMBUS approach consists of a number of traces or transmission lines, each of which transmits a different signal. Ideally, these signal lines are kept in close proximity to one another. One of the signal lines is designated as a reference and used to cancel out some of the noise effects present on the signal lines. A shortcoming of this approach is a noticeable current surge when all of the signal lines are either logic 1's or logic 0's.